Investigation of f_t and f_max in Si and Si_1–xGe_x based single and dual material double-gate Tunnel FETs for RF applications

To meet the scaling demands, many novel devices have been reported with different working principles. Tunnel field effect transistors (TFETs) is one of the promising devices to replace MOSFET because of its sub-threshold swing (SS) limit of 60 mV dec^–1, low OFF-state leakage current and low threshold voltage [1–3]. TFET is basically a reverse biased P–I–N junction diode which works on the principle of quantum mechanical band-to-band tunneling (BTBT) mechanism.

Double gate (DG) TFETs shows improved characteristics in terms of higher drive current and less threshold voltage roll-off compared to single gate TFET [4–6]. A dual material double gate (DMDG) TFET was proposed by using two different gate electrode work functions to improve the overall performance of the device [7, 8]. Since silicon (Si) based DG TFETs suffers from lesser ON-state current, this can be further improved by using lower band gap material like silicon–germanium (SiGe) for the entire region [9], or in the source channel region [10], or in the source only [11–13]. By optimizing mole fraction (x) presented in Si_1−xGe_x, TFET exhibited higher performance with low SS [14, 15].

In this paper the optimization of Si_1−xGe_x based DG TFET is performed to obtain a higher ON state current with lesser SS. To improve the RF metrics, unity gain cut-off frequency (f_t) and maximum oscillation frequency (f_max), the structural parameters are varied for Si and Si_1−xGe_x based single material double gate (SMDG) and DMDG TFETs. Section 2 describes the device structures of Si and Si_1−xGe_x DG TFET along with the simulation methodology. The results are discussed in section 3. Finally section 4 provides the conclusion.

TCAD simulator from Synopsys is used to perform the simulations [16]. Figure 1 depicts the 2D structure of Si and Si_1−xGe_x based n-type SMDG TFET. The schematic diagram of DG TFET is shown in figure 2 which shows various parameters of the device. The device has the gate length (L_g) of 50 nm, a channel thickness (T_ch) of 10 nm, underlap (L_un) of 3 nm and gate oxide thickness (T_ox) of 3 nm. The source is doped with p⁺ type material while the drain is doped with n⁺ type material. The drain doping (N_d = 5 × 10¹⁸ cm⁻³) is lower than source doping (N_s = 1 × 10²⁰ cm⁻³) to suppress the ambipolar effect [17]. The channel has an intrinsic concentration of 1 × 10¹⁷ cm⁻³. The gate electrode work function for SMDG TFET is 4.5 eV.

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The device simulator includes appropriate models for doping dependence mobility, effects of high and normal electric fields on mobility and velocity saturation. A non-local Hurkx BTBT model is used along with Fermi–Dirac statistics and Shockley–Read–Hall recombination model. Supply voltage used in this study is 1 V and the gate voltage is 1.8 V. To operate the device, the source is grounded and the positive voltage is applied at the drain. The gate voltage (V_g) controls the tunneling by modulating the carrier concentration in the channel region. The SS of the device is defined as the change in gate voltage in order to create one decade increase in the output current. It can be expressed as

$$\begin{eqnarray}&&{\rm{S}}{\rm{S}}({\rm{mV}}\;\;{{\rm{dec}}}^{{\rm{-}}1})=\displaystyle \frac{{\rm{d}}{V}_{{\rm{g}}}}{{\rm{d}}({\rm{log}}\;{I}_{{\rm{d}}})}\cdot \end{eqnarray} \tag{ 1 }$$

The TFET ON currents are based on BTBT mechanism. The BTB tunneling probability can be analytically calculated using Wentzel–Kramers–Brillouin (WKB) approximation method. The result of WKB approximation derived in [18] can be described by [19]

$$\begin{eqnarray}&&I\;\infty \;{\rm{exp}}\left(-\displaystyle \frac{4{\rm{\Lambda }}\sqrt{2{m}*}{E}_{{\rm{g}}}^{\mathrm{3/2}}}{3| {e}| \hslash ({\rm{\Delta }}{\rm{\Phi }}+{E}_{{\rm{g}}})}\right){\rm{\Delta }}{\rm{\Phi }},\end{eqnarray} \tag{ 2 }$$

where m* is the effective carrier mass, E_g is the bandgap, e is the electron charge, ΔΦ is the energy range over which the tunneling can take place, $\hslash$ is the Planck's constant and Λ is the spatial extent of the transition at source-channel interface. Λ can be defined by

$$\begin{eqnarray}&&{\rm{\Lambda }}=\sqrt{\displaystyle \frac{{\varepsilon }_{{\rm{S}}{\rm{i}}}}{{\varepsilon }_{{\rm{o}}{\rm{x}}}}{t}_{{\rm{o}}{\rm{x}}}{t}_{{\rm{S}}{\rm{i}}}},\end{eqnarray} \tag{ 3 }$$

where t_ox, t_Si, ε_ox, and ε_Si are the oxide and silicon-film thicknesses and dielectric constants, respectively. Equation (1) shows that the tunneling current can be increased by increasing electric field along the channel (proportional to (ΔΦ + E_g)/Λ). One of the approaches to improve the performance of the device is to decrease the bandgap of the material. The amount of Ge content (x) for the Si_1−xGe_x based DG TFETs improves the ON state current [14, 20]. Figure 3 represents the I_d–V_g characteristics of Si_1−xGe_x based SMDG TFET with Ge mole fraction (x) which is varied from 0 to 0.4. It is observed that the maximum I_on of 23 μA and lesser SS of 32 mV decade^–1 are obtained for x = 0.4. This is because of the lower band gap energy for germanium over silicon. Since lesser SS is obtained for a higher I_on, mole fraction of x = 0.4 is used for SiGe devices.

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Figure 4 shows the energy band diagram for Si and Si_0.6Ge_0.4 based DG TFETs. In the OFF-state (V_g = 0 V), the tunneling barrier width is extremely large enough to give a very small leakage current. When the gate voltage is increased (V_g = 1.8 V), the conduction bands in the intrinsic region are pulled downwards and the tunneling barrier width is reduced allowing electrons move from the source to the channel region [9–11].

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The DMDG TFETs have similar dimensions of SMDG TFETs. To get a fair comparison between Si and Si_0.6Ge_0.4 based SMDG and DMDG TFETs, leakage current (I_off) of all of these devices are matched to 82.7 fA. I_d–V_g characteristics of SMDG and DMDG of Si and Si_0.6Ge_0.4 based TFETs are extracted and plotted in figure 5. It can be seen from the graph that, compared to SMDG, DMDG offers more I_on for both Si and Si_0.6Ge_0.4 based TFETs. This is due to the higher tunneling probability near the source end which enhances I_on significantly [21–23]. Because of the property of double material gate and also due to the tunneling phenomenon, DMDG TFET shows the lower threshold voltage than SMDG TFET [20].

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Figure 6 shows the plot of electron barrier tunneling with respect to distance along the channel for Si and Si_0.6Ge_0.4 based SMDG and DMDG TFETs. The physical significance of this plot represents the rate at which electrons are generated due to tunneling. It can be observed that DMDG TFETs show higher tunneling rate of electrons compared to that of SMDG. Comparatively Si_0.6Ge_0.4 offers more electron tunneling over Si based TFETs.

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For the devices mentioned above, the structural parameters considered here are the gate length, gate oxide thickness, channel thickness and underlap. The important RF parameters, f_t and f_max are extracted by performing AC simulations. f_t is defined as the frequency where current gain becomes unity and in terms of device parameters it can be expressed as

$$\begin{eqnarray}&&{f}_{{\rm{t}}}=\displaystyle \frac{{{g}}_{{\rm{m}}}}{2\pi {C}_{{\rm{g}}{\rm{g}}}},\end{eqnarray} \tag{ 4 }$$

where g_m is the transconductance and C_gg is the combination of gate-source capacitance (C_gs) and gate-drain capacitance (C_gd). f_max is defined as the frequency at which power gain drops to unity and can be expressed as

$$\begin{eqnarray}&&{f}_{{\rm{max}}}\;=\;\displaystyle \frac{{f}_{{\rm{t}}}}{\sqrt{4{R}_{{\rm{g}}}({{g}}_{{\rm{d}}{\rm{s}}}+2\pi {f}_{{\rm{t}}}{C}_{{\rm{g}}{\rm{d}}})}},\end{eqnarray} \tag{ 5 }$$

where R_g is the gate resistance and g_ds is the output conductance.

As mentioned earlier, the gate length, gate oxide thickness, channel thickness and underlap are varied as shown in table 1. The RF parameters, f_t and f_max are extracted for all these devices.

3.1. Variation in gate length

Figure 7 shows the variations of f_t versus L_g. It can be observed that f_t decreases with increasing gate length. Though f_t is determined by both g_m and C_gg, f_t decreases because of g_m degradation for higher gate lengths [24]. Since Si_0.6Ge_0.4 based TFETs offers more g_m comparatively, they exhibits higher cut-off frequencies.

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Figure 8 shows the variations of f_max versus L_g. Compared to f_t, f_max shows higher value because of the inversion layer formed in the drain region and less channel resistance [25]. It can also be observed that f_max increases as gate length decreases for both Si and Si_0.6Ge_0.4 TFETs. This can be attributed to the reduced gate resistance. DMDG TFETs shows lesser f_max compared to SMDG TFETs due to the larger values of g_ds for DMDG TFETs.

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3.2. Variation in oxide thickness

Figure 9 shows the variations of f_t versus T_ox. It can be observed that f_t increases with decreasing gate oxide thickness for both Si and Si_0.6Ge_0.4 TFETs. This can be attributed by the improvement in the gate electrostatic integrity over the channel due to the screening of the electric field at the source side [26]. Si_0.6Ge_0.4 TFETs exhibits higher f_t compared to Si TFETs since the former has more g_m.

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Figure 10 shows the variations of f_max versus T_ox. It can be inferred from the plot that as T_ox decreases, f_max increases due to the smaller gate resistance near the source side and the charge carriers are confined only near the drain region [26].

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3.3. Variation in channel thickness

Figure 11 shows the variations of f_t versus T_ch. It can be observed that f_t increases with decreasing channel thickness. With the scaling of the channel thickness, screening of gate fringing fields dominates, and reduces gate capacitance which ultimately improves f_t [26]. As discussed already, Si_0.6Ge_0.4 TFETs exhibits higher f_t compared to Si TFETs.

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Figure 12 shows the variations of f_max versus T_ch. The increase in f_max can be reasoned out as the reduction in g_ds for lesser values of channel thickness. This holds the same for both Si and Si_0.6Ge_0.4 TFETs.

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3.4. Variation in underlap

Figure 13 depicts the plot between f_t and L_un for Si and Si_0.6Ge_0.4 SMDG and DMDG TFETs. For all the devices, f_t shows a decreased value for the increase in L_un. This may be due to the decreased g_m values for larger values of L_un [27, 28].

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Figure 14 shows the variations of f_max versus L_un. The plot depicts the decreased values of f_max for higher values of underlap. The effective channel length is wider for the increased underlap and the inversion layer is formed close to the drain region. This increases g_ds which ultimately reduces f_max. This effect is seen for both Si and Si_0.6Ge_0.4 TFETs.

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To enhance ON current for a reduced SS in TFETs, Si_1−xGe_x is optimized and then compared with Si based SMDG and DMDG devices. Four structural parameters—gate length, gate oxide thickness, channel thickness and underlap are considered to study the impact of f_t and f_max in Si and Si_0.6Ge_0.4 SMDG and DMDG TFETs. It can be observed that Si_0.6Ge_0.4 offers more f_t and f_max with respect to the variation in the structural parameters. Higher value of f_max can be attributed to inversion layer formed closely to the drain more than to the source unlike conventional MOSFETs. Hence SiGe TFETs seems to be promising candidate to replace Si TFETs for the future analog/RF applications.

This work is supported by Department of Science and Technology, Government of India under SERB scheme (Grant No: SERB/F/2660).